Integrated circuits often have multiple clock domains. In each clock domain, a domain clock is driven by a clock operating at a particular frequency that is different from the clock frequency of the clocks in other clock domains. An asynchronous clock domain crossing refers to an interface between two of these differently clocked logic domains. Often, logic such as combinatorial logic exists at an asynchronous clock domain crossing in ASIC designs. Logic at asynchronous clock domain crossings is conventionally difficult to verify. This is because the receiving sequential element at the crossing may or may not capture a correct or consistent data value when a transmitting sequential element at the crossing (from the asynchronous clock domain) launches a new value. The incorrect value may be received due to a violation of a set up or hold time at the receiving sequential element (which is known as metastability) or even in the absence of metastability. Without metastability, a clock domain crossing problem may exist if a signal change randomly arrives either before or after the metastable period, or may occur due to races between parallel paths of the logic, which are known as clock domain crossing glitches.
Various simulation tools exist in the art to help reveal these types of problems. These simulation tools identify where logic signals cross over between domains and typically insert a simulation model in the signal path that generates a random logic value (0 or 1) during periods of potential inconsistency. This random logic generation is often called jitter when discussing clock domain crossings. Many designers at electronic design automation companies also do this manually by inserting specially designed Wire Asynchronous Models (WAMs) into their logic. The advantage of simulation tools is that they do this automatically.
FIG. 1A depicts one embodiment of an asynchronous clock domain crossing, generally denoted 100, wherein a transmitting sequential element 110 (e.g., latch) of a first clock domain launches logic values through combinatorial logic 120 to a receiving sequential element 130 in a second clock domain. During modeling, a WAM 140 is often inserted immediately after the transmitting sequential element 110 (as shown in FIG. 1B) to facilitate modeling of metastability. Traditional simulation tools (employing WAMs) do a good job at identifying clock domain crossing metastability problems in cases where a signal changes intermittently either before or after the period of metastability. However, existing simulation approaches often do not correctly identify problems caused by clock domain crossing glitches.